This invention relates to a ferroelectric nonvolatile memory and more particularly to a ferroelectric nonvolatile memory having ferroelectric capacitors connected to the gates of field effect transistors of MOS or MIS structure (ferroelectric-gate FET) and a readout method for reading out information from the memory.
If a junction is made between semiconductor and ferroelectrics, it is expected that states in which holes and electrons are respectively induced on the semiconductor surface depending on the polarization direction of the ferroelectrics occur. Therefore, an attempt is already made to set the above two states to correspond to "0" and "1" and form a nonvolatile memory in which the memory contents will not be erased even if the power supply is turned OFF by use of ferroelectrics for forming the gate insulating film of the MOS field effect transistor. However, a device which can be practically used is not realized up to the present time. The most important reason why it is difficult to form the device of this structure is that a necessary current will not flow between the source and drain of the field effect transistor since traps are generated at the interface to capture holes and electrons, if the semiconductor and ferroelectrics are bonded together.
In order to solve the above problem, an MFIS (M: metal or conductor, F: ferroelectrics, I: insulator, S: semiconductor) structure having a dielectric (paraelectric) film such as a silicon dioxide (SiO.sub.2) film which makes it difficult to generate interfacial traps between the ferroelectric film and the semiconductor substrate and an MFMIS structure further having a conductive film between the ferroelectric film and the dielectric film are proposed. The MFIS structure is disclosed in, for example, IEEE ELECTRON DEVICE LETTERS, VOL. 18, NO. Apr. 4, 1997 pp. 160-162 TOKUMITSU et al. "Nonvolatile Memory Operations of Metal-Ferroelectric-Insulator-Semiconductor (MFIS) FET's Using PLZT/STO/Si(100) Structures" and the MFMIS structure is disclosed in, for example, Jpn. J. Appl. Phys. Vol. 38 (1999) pp. 2285-2288 Part 1, No. 4B, April 1999 FUJIMORI et al. "Properties of Ferroelectric Memory FET Using Sr.sub.2 (Ta,Nb).sub.2 O.sub.7 Thin Film".
However, if a laminated structure of the ferroelectric film and the dielectric film is used as the gate insulating film of the field effect transistor, new problems that (1) the programming voltage of information becomes high, (2) information holding time (data retention time) becomes short and the like occur. The problems are described in detail below.
First, the problem that the programming voltage becomes high is explained by taking a concrete structure as an example. Assume that a semiconductor substrate is composed of Si, the ferroelectric film is composed of lead titanate zirconate (PZT: PbZr.sub.1-x Ti.sub.x O.sub.3), and the dielectric film is composed of SiO.sub.2. The same explanation may be applied to a case of the MFIS structure, but the MFMIS structure is used as the gate electrode structure to prevent mutual diffusion of Pb atoms in the PZT film and Si atoms in the SiO.sub.2 film in a case of materials used in this example. The dielectric constant of SiO.sub.2 is 3.9 and the dielectric constant of PZT is set to approx. 200 to 600 depending on the composition ratio of Zr and Ti, and the explanation is made by assuming that the dielectric constant thereof is 390 for simplicity. Further, as the general assumption, the thickness of the SiO.sub.2 film is 1/10 of that of the PZT film.
Since the capacitance of the capacitor is proportional to the dielectric constant of the insulating film provided between the electrodes and inversely proportional to the film thickness of the insulating film, the ratio between the capacitances of the ferroelectric capacitor and the dielectric capacitor becomes 10:1. Further, when the two capacitors are connected in series and a voltage is applied thereto, voltages applied to the respective capacitors are inversely proportional to the capacitances of the capacitors, and therefore, the voltage applied to the ferroelectric capacitor is 1/10 of the voltage applied to the dielectric capacitor, that is, 1/11 of the whole voltage. Therefore, if the MFS structure in which the PZT film is directly deposited on the Si substrate can be formed and the polarization of the film can be reversed by application of 5V, a voltage which is as high as 55V is necessary to attain the polarization reversal when the MFMIS structure is formed with the same film thickness.
Next, the problem that the information holding time becomes short is explained with reference to the drawing. If the MFMIS structure is expressed by use of an equivalent circuit, a structure in which a ferroelectric capacitor C.sub.F and a dielectric capacitor C.sub.I, are connected in series can be attained as shown in FIG. 1A. In this case, the depletion layer capacitance of the semiconductor is not considered and it is assumed that the entire portion of the semiconductor is kept at the ground potential.
Assuming that a voltage V is applied to the upper-side electrode, voltages of V.sub.F, V.sub.I are respectively applied to the capacitors C.sub.F, C.sub.I. At this time, the following equation can be attained. EQU V.sub.F +V.sub.I =V (1)
If the charge amount appearing on both electrodes of the ferroelectric capacitor C.sub.F is .+-.Q, the charges of .+-.Q appear on both electrodes of the dielectric capacitor C.sub.I, as shown in FIG. 1A under a condition that the total amount of charges on the connecting portion between the two capacitors C.sub.F, C.sub.I must be set to 0. Further, since the relation "Q=C.sub.I V.sub.I " is set in the dielectric capacitor C.sub.I, the following equation can be obtained by substituting the equation (1). EQU Q=C.sub.I (V-V.sub.F) (2)
As indicated by the curve LA1 of FIG. 1B, it is known that the relation between Q and V.sub.F of the ferroelectric capacitor C.sub.F exhibits hysteresis. If the relation of the equation (2) is superposed on FIG. 1B, the straight line LA2 can be obtained as shown in FIG. 1B and intersections between the two lines indicate a voltage applied to the ferroelectrics and the amount of charges appearing on the electrode of the capacitor. The position A in FIG. 1B indicates Q and V.sub.F when a high voltage is applied in the positive direction and then the voltage is kept at V and the position B indicates Q and V.sub.F when a high voltage is applied in the negative direction and then the voltage is kept at V.
Therefore, if a high voltage is applied in the positive direction and then the voltage is returned to 0, Q and V.sub.F of the ferroelectric capacitor indicated by the position C are set and the direction of polarization and the direction of electric field are opposite to each other. That is, if information is held by returning the gate voltage to 0 after the programming operation is effected by applying a positive voltage to the gate electrode of the field effect transistor having the MFIS or MFMIS gate structure, the electric field in the opposite direction to the direction of the polarization is applied to the ferroelectrics and the remnant polarization amount disappears in a brief period of time. Particularly, when the capacitance of the dielectric capacitor serially inserted is small, the magnitude of the electric field in the opposite direction becomes closer to coercive electric field (which is required to return the polarization amount to 0) and the polarization retention time becomes extremely short.
The problem that the holding time is short cannot be neglected not only in the MFIS or MFMIS structure but also in the MFS structure in some cases. That is, the depletion layer capacitor formed on the semiconductor surface and the ferroelectric capacitor form a series-connected capacitor depending on the bias condition and substantially the same problem as that occurring as shown in FIG. 1B occurs.
Thus, in the conventional nonvolatile memory using the ferroelectrics for forming the gate insulating film of the MOS field effect transistor, it is necessary to use the MFIS or MFMIS structure so as not to generate interfacial traps between the semiconductor substrate and the ferroelectric film. However, if this type of structure is used, there occurs a problem that a voltage for programmed information becomes high and the information holding time becomes short.